With the increasing down-scaling of integrated circuits, metal-oxide-semiconductor field-effect transistors (MOSFET) need to be increasingly smaller, with increasingly shorter gates. This requires the junctions, particularly the junctions between lightly doped source/drain regions and pocket regions, to be shallower. However, due to the diffusion of the implanted impurities, it is very difficult to reduce the depth of the junction to about 50 Å for short channel effect control (SCE), which is a preferred junction depth for future small-scale MOSFETs.
What makes the reduction of junction depths more difficult is that for smaller MOSFETs, the pocket regions need to have higher impurity concentrations. However, with heavier pocket implantations, several adverse effects may be resulted. For example, although the short channel effect (SCE) and drain-induced barrier lowering (DIBL) may be better, the carrier mobility of the carriers in the channel region is degraded, resulting in smaller device drive currents.
To solve these problems, silicon-on-nothing (SON) MOSFETs have been proposed. SON MOSFETs have air-gaps under channel regions. With the air-gaps, the SCE of the SON MOSFETs is improved, and leakage currents can be reduced. However, the processes for forming the SON MOSFETs face challenges. For example, a process was proposed by Toshiba to form the air-gaps. The process includes forming parallel trenches in a silicon substrate, and annealing the silicon substrate to form an air-gap, wherein the anneal causes the migration of silicon, and a layer of silicon seals the air-gap. The drawback of this process is that the thickness of the silicon layer over the air-gap is greater than desirable, and the thickness of the silicon layer may reach about 0.3 μm, which is far greater than the desirable thickness for example, less than 150 Å. In addition, it is hard to control the final thickness of the silicon channel. For process reasons, it is difficult to reduce the thickness of the silicon layer on the air-gap.
Another conventional process includes forming a silicon germanium layer on a silicon substrate, forming a silicon layer on the silicon germanium layer, forming a gate over the silicon layer, forming source and drain recesses, and etching the silicon germanium layer to form the air-gap. This process appears to solve the above-discussed problems. However, up to now, process difficulties prevented the implementation of the idea on silicon substrate. The reason was that during the subsequent filling of the source and drain recesses, the filing material was undesirably grown in the air-gap, and hence the air-gap was refilled. New methods are thus needed to form MOSFETs with SON structures.